A 1.8 V Monolithic CMOS Nested-Loop Frequency Synthesizer for GSM Receivers at 1.8 GHz

A low-power, integrated 1.8 GHz nested-loop frequency synthesizer for GSM at 1.8 GHz in a 0.18 μm CMOS technology is presented. The synthesizer consists of two voltage-control oscillators (VCOs) and uses band switching MIM capacitors and analog tuning circuits using pMOS capacitors. Both VCOs and loop-filters are integrated on-chip. The IF VCO phase noise is −131 dBc/Hz@600kHz from a 450 MHz carrier and the RFVCO phase noise is −121 dBc/Hz@600kHz from a 1.8 GHz carrier. The power consumption of this nested-loop frequency synthesizer is 36mW@1.8V and has a die size of 3000 μm × 2000 μm.