Conference
A 1.8 V Monolithic CMOS Nested-Loop Frequency Synthesizer for GSM Receivers at 1.8 GHz
Abstract
A low-power, integrated 1.8 GHz nested-loop frequency synthesizer for GSM at 1.8 GHz in a 0.18 μm CMOS technology is presented. The synthesizer consists of two voltage-control oscillators (VCOs) and uses band switching MIM capacitors and analog tuning circuits using pMOS capacitors. Both VCOs and loop-filters are integrated on-chip. The IF VCO phase noise is −131 dBc/Hz@600kHz from a 450 MHz carrier and the RFVCO phase noise is −121 …
Authors
Murji R; Deen MJ
Pagination
pp. 291-294
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2003
DOI
10.1109/rfic.2003.1213946
Name of conference
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003