Conference
A low-power wideband frequency doubler in 0.18 /spl mu/m CMOS
Abstract
The paper presents a new design technique for a wideband, low-power implementation of a frequency doubler in a 0.18 /spl mu/m CMOS technology. The frequency doubler consists of two identical unbalanced source-coupled pairs, whose inputs are connected in parallel and its output taken single-ended. The design is based on the quadratic square-law characteristics of a MOS transistor in saturation. The frequency doubler operates at a low supply …
Authors
Murji R; Deen MJ
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
January 1, 2005
DOI
10.1109/iscas.2005.1465595
Name of conference
2005 IEEE International Symposium on Circuits and Systems
Conference proceedings
2005 IEEE International Symposium on Circuits and Systems (ISCAS)
ISSN
0271-4302