MOSFET Modeling for Low Noise, RF Circuit Design

In this paper, high frequency (HF) AC and noise modeling of MOSFETs for low noise, radio frequency (RF) integrated circuit (lC) design are discussed. Scalable parasitic model and the Non-Quasi-Static (NQS) model are discussed and verified with the measured data. For the noise modeling, extracted noise sources of MOSFETs in $0.18 \mu {\rm m}$ Cmos process and from RF noise measurements are presented. Finally, the design consideration including selection of device size, bias condition and design of the device geometry are discussed.