Optimal Low Switching Frequency PWM Pattern for a Three-Level Neutral Point Clamped (NPC) Inverter

This paper proposes a mechanism of development of synchronous optimal pulse width modulation (PWM) generation for control of medium-voltage motor drives using multilevel inverters at low switching frequency. Multilevel inverters enable operation with multiple dc-link voltages while lowering total harmonic distortion (THD). Thermal losses limit the maximum switching frequency in high-power applications. As a result, the output waveforms are highly distorted. Synchronous optimal PWM (SOP) control allows for a low maximum switching frequency without sacrificing THD. The switching losses of power semiconductor devices are reduced when the switching frequency is low. A detailed explanation of an optimal control procedure is provided. The paper investigates the implementation of the SOP scheme in a three-level inverter topology and is compared with a two-level inverter. Also, the performance of SOP and in-phase disposition (IPD) modulation schemes are evaluated on a three-level neutral point clamped inverter with a switching frequency of 420Hz. The findings indicate that SOP improves the results of IPD for low switching frequencies. This demonstrates that the SOP is very useful in high power applications, resulting in a significant reduction in the use of bulky and expensive filtering elements.