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Session 38 Solid-State and Nanoelectronic Devices...
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Session 38 Solid-State and Nanoelectronic Devices - Active and Passive Components in CMOS-Compatible Technologies

Abstract

This session covers some important active and passive components that are created in CMOS-compatible technologies, and are suitable for current and emerging silicon-based electronic systems. The first paper introduces the design principles, processing techniques and experimental characteristics of tunable on-chip inductors using high-m permalloy thin films. These inductors, working up 5 GHz, had quality factors between 5 and 11 and up to 15% tuning range. An important component for wireless communications is small-size antennas working at high frequencies. The second paper discusses a compact on-chip monopole antenna capable of working in the 5.8GHz ISM band and with a 30m communication range. An important challenge facing the semiconductor industry is the large standby leakage power due mostly to high subthreshold currents in CMOS devices. The third paper presents results on a novel impact ionization L-shaped MOS (LI-MOS) transistor that is compatible with standard CMOS technology with the impressive room-temperature subthreshold slope of 4.5mV/decade from a 100nm channel length device. The fourth paper integrates a 70nm impact-ionization MOSFET with a 70nm tunneling FET to create both low-power and high-performance functionality on the same chip. Impressive results in on/off current ratios and static noise margins are demonstrated. The fifth paper explores the use of a novel SiGe negative differential resistance (NDR) device to create DRAMs and SRAMs in a CMOS-compatible technology. The functionality of both types of memory elements are demonstrated through experiments and simulations. The final paper in this session presents a low-cost SiGeC HBT module suitable for RF CMOS platforms in either bulk silicon or SOI technologies. This HBT architecture meets the low-cost challenge of very high-performance silicon-based heterostructure technologies since only four additional masks were needed and it also is compatible with thin SOI substrates.

Authors

Kiyota Y; Deen J

Pagination

pp. 942-942

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

January 1, 2005

DOI

10.1109/iedm.2005.1609515

Name of conference

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.
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