Post-processing of Commercial CMOS Chips for the Fabrication of DNA Bio-FET Sensor Arrays

A BioFET array can be fabricated by post-processing of a standard CMOS chip if temperatures are kept below 450 °C and radiation or ion-bombardment damage is minimized. The processing starts with encapsulation by deposition of a low stress, electrolyte-impermeable silicon nitride layer by PECVD at 375 °C. Anisotropic reactive ion etching with an inductively coupled plasma using C4F8 and Ar was used to remove the silicon nitride and oxide layers above the poly-silicon gates. The poly-silicon was then etched off using a selective wet etch. The effect of the processing was characterized by making current-voltage and capacitance-voltage measurements with MOS capacitor structures at each stage of processing and results showed that trapped charges or interface states could be annealed out at low temperatures. Scanning electron microscopy was used to examine the cross-section of the gate areas after the etching. The results of current-voltage measurements with a Ag/AgCl reference electrode on devices in electrolyte solutions were compared to the results of charge-sheet model calculations including the effect of amphoteric charging sites on the oxide and the potential drops in the electrolyte. Measurements showing the threshold shifts subsequently produced by DNA probe attachment and hybridization will also be presented.