DC and Low-Frequency Noise Optimization of Four-Gate Transistors

The effects of different parameters on the DC and low-frequency noise performance of four gate field effect transistors (G4-FET) are studied. Experimental data of the drain current and the current noise power spectral density (PSD) are compared with simulation results. The comparisons show that the drain current and its associated noise are very sensitive to the doping profile of the pn junctions that constitute the lateral gates of the device. The presence of recombination centers also modifies the performance of the device. These centers can degrade the excellent subthreshold slope that the G4-FET transistor exhibits. At the same time, the generation-recombination (g-r) noise produced by deep traps in the depletion regions of the device can be reduced by the presence of these recombination centers. In this work, we propose a procedure to determine an optimal dopant profile of the lateral pn junctions of the device that minimizes the subthreshold slope and the low frequency noise and maximizes the transconductance.