Low-Power Integrated CMOS RF Transceiver Circuits for Short-Range Applications

This paper discusses our efforts in designing different low-power RF transceiver blocks, starting with the LNA and power amplifier (PA). The paper discusses the effect of four different input matching methodologies on the gain of narrow-band LNAs. Measurement results of two LNAs fabricated in a ${\bf 0.18}\ {\mbi \mu} {\bf m}$ CMOS technology are also presented. Two ultra-wideband (UWB) LNA designs that aim for low-voltage and low-power operation are also discussed in this paper. The UWB LNAs consume a power of 5.8 mW from a 0.8 V supply voltage, while achieving a maximum gain of 12.5 dB and an input matching better than −10 dB from 2–10 GHz with a NF of 3.5 dB. A fully integrated, 2.4 GHz class-E PA, with a class-F driver stage is also discussed in this work, demonstrating the feasibility of using CMOS class-E PAs for low-transmit power applications. The circuit was fabricated in a standard ${\bf 0.18}\ {\mbi \mu} {\bf m}$ CMOS technology with a maximum drain efficiency of 53 %. When operating from a 1.2 V supply, the PA delivers an output power of 14.5 mW with a power-added efficiency (PAE) of 51 %. The supply voltage can go down to 0.6 V with an output power of 3.5 mW and a PAE of 43 %. Finally, the paper also discusses a simple transmitter and receiver front-end, in addition to a single-block simplified, low-power PLL transmitter design.