Systematic Design and Development Procedures for a Successful CMOS LNA Implementation

Through this work we highlighted and demonstrated the significance of an algorithmic way of design and development of CMOS LNAs at 5 GHz. The systematic design led to very good measured performances of 14 dB gain, 1.78 dB noise figure, 10 dB return loss both at the input and output and a high linearity of −3 dBm of IP3 under 5.4 mW power consumption. These results compare the best performances reported in 5 GHz CMOS LNAs [3]–[7]. Further it was shown, that this design and development approach is able to achieve state-of-the-art measured performances with very good agreement with the simulated results.