Ever since the discovery of the photon by Einstein and Planck, scientists have continually strived to achieve single photon imaging; considered the holy grail of photosensing, since it represents the ultimate detection and precision limit of electromagnetic radiation. With the invention of the photomultiplier tube (PMT) in the 1930s, single-photon detection became feasible. Since then, PMTs have been developed to meet a wide range of application needs. For the most demanding time-resolved measurements, micro-channel plate (MCP) PMTs have been used. However, PMT devices are inherently limited due to their large size, high-cost, fragility, high operating voltages, and magnetic field susceptibility. On the other hand, Geiger-mode APDs realized in CMOS technology do not suffer from these limitations, and in recent years, their performance has significantly improved so they are now comparable to PMTs. As such, single photon imagers based on CMOS single-photon avalanche detectors (SPAD) have been realized for applications where speed, cost, miniaturization and power consumption are critical .
The main components of a high-speed single photon imaging system is the SPAD, which converts a single photon to an electrical pulse, the SPAD front-end circuit, which shapes the pulse and controls the SPAD, and the time-to-digital converter (TDC), which converts the time interval between the detected photon and a reference pulse, or the time between two detected photons, into a digital code. Deep sub-micron (DSM) CMOS technology lends itself very well to the realization of such a system; all the components can be integrated together with very high reliability at a very low cost, digital processing can be readily applied to the detected photons, and dense arrays can be realized for multi-dimensional processing. Over the last decade, CMOS single-photon imaging systems have been applied in the fields of biomedical research, astronomy, nuclear physics, ranging and communications , , .
This work describes the design of the main components of a high-speed single photon imaging system for biomedical applications, implemented in a standard, commercial CMOS 0.13 μm technology from IBM. A passively-quenched SPAD pixel was characterized in terms of its noise, temporal resolution, efficiency, and temperature performance. By fabricating the SPAD in a DSM technology, we were able to take advantage of the inherent speed, lower parasitic capacitance, and increased integration density afforded by the CMOS process. Indeed, a dead-time down to 20 ns was achievable with the SPAD front-end circuit, since the total capacitance of the 9.6 x 8.5 μm2 SPAD remained below 100 fF. Also, a new dual-interpolating tapped-delay-line TDC prototype chip was designed and evaluated for a future integration with an SPAD in a multichannel fluorescent lifetime imaging / positron emission tomography (FLIM/PET) system. The design goals were to achieve simultaneously a high-resolution, high throughput, good linearity, wide measurement range, small size and low power. The 8-bit TDC chip measures time intervals with a 156 ns least-significant bit (LSB) between a common STOP pulse from a laser and a START pulse generated by an SPAD, as in a typical time-correlated single-photon counting (TCSPC) acquisition chain shown in figure 1. In this presentation, details of the key design issues and the results from extensive testing will be provided and discussed.
 Cova, S.D.; Ghioni, M.,
IEEE Photon. J., vol.3, no.2, pp.274-277, April 2011
 Markovic, E.; Tisa, S.; Tosi, A.; Zappa, F.,
Proc. SPIE, vol. 8033, no. 80330A, 2011
 Maruyama, Y.; Blacksberg, J.; Charbon, E.,
Proc. IEEE Int. Solid-State Circuits Conf.,pp.110-111, 2013
 Fisher, E.; Underwood, I.; Henderson, R.,
IEEE J. Solid-State Circuits, vol.48, no.7, pp.1638-1650, 2013