A Framework for Practical Design of Switching Nodes with Parallel-Connected MOSFETs

The number of high current carrying interfaces originating from power-dense electronic sub-systems is increasing with the rise of electrified transportation. The order of magnitude of currents handled by these interfaces is in hundreds of amperes, and is generally beyond the power-handling capability of a single power switch. To manage these high current levels, discrete switch paralleling is a preferred practice compared to usage of power modules for two reasons; flexibility in packaging based on available thermal interfaces, and eliminating the need to over-design the solution. While the challenges in MOSFET paralleling and their mitigation techniques have been addressed in literature, this paper focuses on presenting a generalized framework that can be applied for the practical design of any switching node with parallel-connected MOSFETs. Utilizing this design framework aims to reduce the risk of revising hardware designs due to non-compliance with performance expectations on the electrical and thermo-mechanical fronts.