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Dimensionality reduction for the on-chip...
Conference

Dimensionality reduction for the on-chip integration of advanced photonic devices and functionalities

Abstract

Design of modern photonic devices requires to handle a large number of parameters and figures of merit. By scaling down the complexity of the problem, machine learning dimensionality reduction enables the discovery of better performing devices, higher integration scale, and efficient evaluation of fabrication tolerances.

Authors

Melati D; Dezfouli MK; Grinberg Y; Al-Digeil M; Xu D-X; Schmid JH; Cheben P; Waqas A; Manfredi P; Zhang J

Volume

00

Pagination

pp. 1-4

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

January 16, 2021

DOI

10.1109/ecoc52684.2021.9606084

Name of conference

2021 European Conference on Optical Communication (ECOC)