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DC and Thermal Noise Modeling of 20 nm Double-Gate...
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DC and Thermal Noise Modeling of 20 nm Double-Gate Junctionless MOSFETs

Abstract

Junctionless field-effect transistors (FETs) are now actively pursued as a future silicon transistor technology because of its good scalability, excellent electrical performance and relatively simple structure. There has been much research and technology development in JL FETs, their modeling, including some compact modeling, but relatively little work in modeling both noise and static characteristics. In this paper, we present an improved dc …

Authors

Jeong E-Y; Jeong Y-H; Chen C-H; Deen MJ

Pagination

pp. 1-4

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

June 1, 2013

DOI

10.1109/icnf.2013.6578976

Name of conference

2013 22nd International Conference on Noise and Fluctuations (ICNF)

Labels

Fields of Research (FoR)