Noise Characterization and Modeling of MOSFETs for RF IC Applications Theses

This thesis develops a systematic and self-consistent framework for the RF noise characterization, modeling and simulation of deep sub-micron MOSFETs. The techniques and procedures developed in this thesis are general and can be applied to the high-frequency noise characterization of any active device. In general, there are five topics presented in this research work. First, a systematic calculation method that can directly calculate the noise parameters - minimum noise figure NFmin, equivalent noise resistance Rn, optimized source resistance Ropt and reactance Xopt - of an active device using matrix computation is presented. This method is general and can calculate the noise parameters of any noisy two-port network including correlated noise sources.

Second, a new de-embedding procedure based on a cascade configuration to remove the parasitic effects of the probe pads and the metal connections from the measured noise and s-parameters is developed. Two "THRU" dummy structures are proposed in the new de-embedding procedure and no equivalent circuit models for the probe pads and the interconnections are required. From theory, it has no frequency limitation (or it is valid to the frequency at which the discontinuity effect has to be taken into account) and works for any geometry of interconnection designed without introducing more dummy structures.

Third, two extraction methods to obtain the spectral densities of the channel noise, induced gate noise and their noise correlation from the intrinsic noise parameters as a function of frequency and bias condition are presented. The extracted noise spectral densities of desired noise sources will serve as a direct target for the verification of any proposed noise model developed.

Fourth, new physics-based channel noise models to predict the channel noise, induced gate noise and their noise correlation are developed and verified with the extracted noise sources. The impact of the channel-length modulation (CLM) effect, the hot electron effect, and the velocity saturation effect on the desired noise sources in the deep sub-micron MOSFETs are discussed in detail.

Lastly, the design strategies of a low noise amplifier based on the developed noise models and extracted noise information are presented as a guide line to choose the device size and bias condition of the transistors. The impact of the model accuracy on the simulated noise performance of a two stage low noise amplifier is also presented.