Power dissipation is now both a key constraint and an application driver in VLSI systems. For a specific application, the energy efficiency of different implementations can differ by multiple orders of magnitude. This work surveys a range of techniques available to improve energy efficiency and highlights their cumulative benefit. Understanding, adopting and adapting selected techniques from full-custom solutions can help bridge the efficiency gap for the ASIC designs. Architecture and micro-architecture choices yield multiple-order of magnitude improvements in power dissipation by matching the structure of the design to the structure of the application and by providing multiple operating and power-down modes. The combination of methodology and full-custom circuit techniques and libraries provide benefits primarily due to reduced parasitic loading enabling the improved performance to be translated into the potential for factor-of-3 to factor-of-10 improvements in power.