Conference
Linearity and Intermodulation Distortion Assessment of Underlap Engineered Cylindrical Junctionless Surrounding Gate MOSFET for Low Noise CMOS RFIC Design
Abstract
In this paper the reliability of Junctionless Surrounding Gate MOSFET has been examined by investigating the effect of underlap engineering on the linearity and intermodulation distortions in order accredit the device efficacy for Low Noise SOC design for wireless applications. Linearity metrics namely VIP3, gm3, IMD3, VIP2, IIP3 and 1 dB compression point have been studied for CJLSG MOSFET with and without gate underlap engineering (for …
Authors
Rewari S; Goel A; Verma S; Gupta RS
Volume
00
Pagination
pp. 1-4
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
December 15, 2019
DOI
10.1109/indicon47234.2019.9029025
Name of conference
2019 IEEE 16th India Council International Conference (INDICON)