A Low-Power Dual-Band WLAN CMOS Receiver

A dual-band, dual-conversion receiver integrated from LNA to analog baseband circuitry is presented. The low-pass filters integrate a cutoff frequency auto calibration scheme and can be automatically tuned from 6-MHz to 17-MHz with $\pm {\bf 3}\hbox{\%}$ accuracy. This design is suitable for multi-standard, multi-bandwidth applications, such as 802.11a/b/g and the incoming 802.11n, while the RF front-end is shared. The chip was fabricated in TSMC 0.25um CMOS process with 2.5V power supply. The noise figure is 2.8dB/3.9-dB for 2.4/5-GHz bands at the maximum gain setting, and the iIP3 of 10/-3-dBm is achieved for 2.4/5-GHz bands at the minimum gain. The receiver provides a programmable gain of 88/78-dB in 2dB steps and consumes 51/54-mA current for 2.4/5-GHz bands, respectively.