Hardware implementation of the optimized transform and quantization blocks of H.264

H.264 also known as MPEG 4 part 10 or JVT, is a new video coding standard that is extremely efficient and is poised to appear in the next generation of HD-DVD players and recorders. This paper presents one of the first hardware architectures of the transform and quantization blocks, which are incorporated into a software/hardware system implemented on a Virtex II Pro FPGA. This implementation focuses on eliminating drift effects, multiply free and low gain transform, and reducing memory bandwidth. A large system on a programmable chip was developed. It uses a Power PC (PPC) to run a software program to optionally perform DCT and quantization in both the software and hardware. This paper presents DCT and quantization blocks that can process about 1500M pixels/s, and a system that can process about 0.8 Mpixels/s.