Conference
Thermal Noise Performance in Recent CMOS Technologies
Abstract
This paper reviews the measurement and modeling issues of the channel thermal noise in MOSFETs as a result of the aggressive reduction of the channel length into the sub-100 nm regimes. It also shows the noise performance of devices in 65 nm CMOS technology.
Authors
Chen C-H; Hung B; Huang S-Y; Jan J-S; Liang V; Yeh C-S
Pagination
pp. 476-479
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
October 1, 2008
DOI
10.1109/icsict.2008.4734584
Name of conference
2008 9th International Conference on Solid-State and Integrated-Circuit Technology