Conference
Channel Thermal Noise and its Scaling Impact on Deep Sub-100nm MOSFETs
Abstract
In this paper, we present the noise behavior of deep sub-100 nm bulk MOSFETs in 60 nm devices and predict that down to 17 nm. Analytical MOSFET channel thermal noise models are presented and calibrated using experimental data from 60 nm devices. Technology scaling issue on noise performance is also examined by applying the technology parameters presented in International Technology Roadmap for Semiconductors (ITRS) 2009 edition. Simulation …
Authors
Tan G; Chen C-H; Hung B; Lei P; Yeh C-S
Pagination
pp. 356-359
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
June 1, 2011
DOI
10.1109/icnf.2011.5994342
Name of conference
2011 21st International Conference on Noise and Fluctuations