Channel Thermal Noise and its Scaling Impact on Deep Sub-100nm MOSFETs

In this paper, we present the noise behavior of deep sub-100 nm bulk MOSFETs in 60 nm devices and predict that down to 17 nm. Analytical MOSFET channel thermal noise models are presented and calibrated using experimental data from 60 nm devices. Technology scaling issue on noise performance is also examined by applying the technology parameters presented in International Technology Roadmap for Semiconductors (ITRS) 2009 edition. Simulation results show that the noise improvement stops at around 29 nm technology node due to the increased gate resistance. Increasing the finger number is necessary to retain noise improvement in future technology nodes.