Future Low-Noise Technologies for RF, Analog and Mixed-Signal Integrated Circuits

In this paper, we evaluate the noise performance of future nano-scale MOSFETs fabricated using strain engineering technique, channel engineering with III-V materials, and quantum-well structures for low noise, low power radio-frequency (RF), analog and mixed-signal integrated circuit (IC) designs. We conduct this study utilizing our recently defined equivalent noise sheet resistance. We present the experimental results for devices fabricated in UMC's 65 nm, 40 nm and 28 nm CMOS technology nodes and other recently published results down to the 18 nm technology node.