Conference
Future CMOS Technology for Low Noise Integrated Circuit Designs
Abstract
This paper utilizes the recently defined equivalent noise sheet resistance to study the noise performance of future sub-l00nm MOSFETs using strain engineering, channel engineering with 111-V materials, and quantum-well structures for low-noise applications. Experimental results for devices fabricated in UMC's five different CMOS technology nodes and other published data down to 20 nm technology node are demonstrated. Strategies for the future …
Authors
Chen C-H; Wu DY; Cheng YC; Chen CS
Pagination
pp. 1-4
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
October 1, 2014
DOI
10.1109/icsict.2014.7021277
Name of conference
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)