Gate Technology Issues for Silicon Mos Nanotransistors Conference Paper uri icon

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  • AbstractThis article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm


  • Tennant, DM
  • Timp, GL
  • Ocola, LE
  • Green, M
  • Sorsch, T
  • Komblit, A
  • Klemens, F
  • Kleiman, Rafael
  • Muller, DA
  • Kim, Y
  • Timp, W

publication date

  • 1999