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Index Assignment Capable of Detecting One Bit...
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Index Assignment Capable of Detecting One Bit Errors for Multiple Description Scalar Quantizers

Abstract

This work is concerned with increasing the error resilience of two description scalar quantizers by applying a permutation to the index of each description, for an m-diagonal initial index assignment. First we address the existence of permutations achieving a minimum Hamming distance of at least 2. Such permutations allow the central decoder to detect any 1 bit error pattern. We establish the connection with the hypercube antibandwidth problem, connection which allows us to determine the highest value of m for which such a permutation exists and to show its construction. Further, we highlight the relation between the error robustness at the side decoders and the bandwidth of the hypercube labeling associated to the permutation. To ensure error resilience at both the central and side decoders we are interested in labelings with the lowest bandwidth given that the antibandwidth is larger or equal to m. We make some progress toward the solution of this problem by constructing a class of hypercube labelings trading the increase in antibandwidth for the decrease in bandwidth.

Authors

Wan Y; Dumitrescu S

Pagination

pp. 55-60

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

June 1, 2013

DOI

10.1109/cwit.2013.6621592

Name of conference

2013 13th Canadian Workshop on Information Theory
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