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Visualisation of Partial Order Models in VLSI...
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Visualisation of Partial Order Models in VLSI Design Flow**Project on model visualisation MOVIE, EPSRC grant GR/M94366

Abstract

Summary form only given. A new method, algorithms and tool for the visualisation of a finite complete prefix (FCP) of a Petri net (PN) or a signal transition graph are presented. A transformation is defined that converts such a prefix into a two-level model. At the top level, it has a finite state machine (FSM), describing modes of operation and transitions between them. At the low level, there are marked graphs, which can be drawn as waveforms, embedded into the top level nodes. The models of both levels are abstractions traditionally used by electronics engineers. The resultant model is completed trace equivalent to the original prefix. Moreover, the branching structure of the latter is preserved as much as possible

Authors

Bystrov A; Yakovlev A; Koutny M

Pagination

pp. 1089-1089

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

January 1, 2002

DOI

10.1109/date.2002.998446

Name of conference

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition
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