This paper describes results of our investigation on the hysteresis phenomenon observed in multiple-peak resonant tunneling devices based on a series combination of resonant tunneling diodes (RTDs). We have modelled this hysteresis by assuming that when one of the diodes in the series combination is switching from its prenegative differential resistance (NDR) region to its post-NDR region or back, the others are acting as a combined load to it. Our analytical model based on a load-line analysis with a piecewise-linear approximation for the RTD I–V curve brings out the salient features of hysteresis as measured on a three-peak device based on discrete RTDs. Also, the model provides a first-order quantitative picture that is particularly useful in the context of difficulties in reliable dc circuit simulation on these devices. We have further shown results of our transient circuit simulation on a four-state memory cell that uses the tree-peak device as its driver and constant current metal semiconductor field effect transistor load device. The simulation results clearly bring out the importance of considering hysteresis in the driver device and its implications on important cell parameters such as logic levels, noise margins, and power dissipation. Finally, we verify the simulation scheme with experimental results from an actual memory cell constructed with discrete RTDs and a constant-current load device.