A low-power wideband frequency doubler in 0.18 /spl mu/m CMOS

The paper presents a new design technique for a wideband, low-power implementation of a frequency doubler in a 0.18 /spl mu/m CMOS technology. The frequency doubler consists of two identical unbalanced source-coupled pairs, whose inputs are connected in parallel and its output taken single-ended. The design is based on the quadratic square-law characteristics of a MOS transistor in saturation. The frequency doubler operates at a low supply voltage of 1 V and consumes 0.985 mW of power at a 3 dB bandwidth of 4 GHz.