Improving the Timing Accuracy of UWB Radars Employing Programmable Delay Chips

The ultrawideband (UWB) radars must realize sampling rates over 20 giga-samples per second (GSa/s) for high-fidelity time sampling of signals with spectrum within the UWB range (3.1–10.6 GHz). The analog-to-digital converters (ADCs) capable of such rates are too expensive for consumer electronics. A low-cost alternative is offered by the equivalent-time sampling receivers (ETSRs), of which those employing programmable delay chips (PDCs) provide the fastest measurements. The off-the-shelf PDCs offer delays as small as 10 ps, which, in principle, allow for sampling rates up to 100 GSa/s. In reality, the temporal digitization precision is compromised by the PDC temperature-dependent delay inaccuracies (as large as up to 520ps), precluding accurate time sampling at or above 20 GSa/s. We quantify the temperature dependence of the PDC delays in situ, i.e., the chip is installed in the ETSR time-sampling circuitry, where a sensor provides its real-time temperature. We propose a calibration method, which improves the radar’s timing accuracy by two orders of magnitude to ~5 ps. Statistical error analysis and UWB pulse measurements with a 5-GHz analog bandwidth PDC-based UWB radar demonstrate the method’s effectiveness.