Accurate High-Speed Equivalent-Time Sampling Receiver: Architecture and Performance Metrics

An equivalent-time (ET) sampling ultra-wideband (UWB) dual-channel receiver is proposed, which is controlled by a field-programmable gate array (FPGA). It has a programmable repetition period and ET sampling rate [up to 20 gigasamples per second (GSa/s)]. The architecture employs a programmable delay chip (PDC) to achieve ultra-high speed of over 8900 traces/s for a typical $1~\mu $ s repetition period. Compared with previously reported high-speed (PDC-based) receivers, it offers superior time-sampling accuracy. The design incorporates a custom dual-channel radio frequency (RF) front end with a low-jitter clock source, critical in achieving time-sampling stability. Importantly, a simple yet effective method is proposed to correct the systematic timebase distortions due to the PDC, whose delay inaccuracies are the main signal-degradation factor in ET receivers realizing picosecond sampling intervals. The realized low-cost system operates as a high-speed oscilloscope with a 10-dB receiver bandwidth of 6 GHz and with accuracy comparable to that of bench-top high-speed oscilloscopes. Performance metrics and measurement procedures are proposed to evaluate and compare time-sampling receivers. These are applied to the proposed receiver, including tests as part of a compact pulsed radar. Its performance is compared with two high-speed bench-top oscilloscopes as well as previously reported ET receiver prototypes.