Impact of silicide layer on single photon avalanche diodes in a 130 nm CMOS process

Single photon avalanche diode (SPAD) is an attractive solid-state optical detector that offers ultra-high photon sensitivity (down to the single photon level), high speed (sub-nanosecond dead time) and good timing performance (less than 100 ps). In this work, the impact of the silicide layer on SPAD's characteristics, including the breakdown voltage, dark count rate (DCR), after-pulsing probability and photon detection efficiency (PDE) is investigated. For this purpose, two sets of SPAD structures in a standard 130 nm complementary metal oxide semiconductor (CMOS) process are designed, fabricated, measured and compared. A factor of 4.5 (minimum) in DCR reduction, and 5 in PDE improvements are observed when the silicide layer is removed from the SPAD structure. However, the after-pulsing probability of the SPAD without silicide layer is two times higher than its counterpart with silicide. The reasons for these changes will be discussed.