Modeling of shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET gate-induced drain leakage (GIDL)

In this paper, an analytical paradigm for the gate-induced drain leakage (GIDL) for shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET using superposition technique with appropriate boundary conditions is proposed. Electric field, Ez, gate-induced drain leakage current, IGIDL, and surface potential have been modeled. The analytical model has been critically examined for different channel lengths, silicon film radii and temperatures. The Arrhenius plot for the gate leakages has also been modeled. The analytical results obtained have been verified with the simulated data. In addition to the analytical results, the curtailment of the band-to-band tunneling (which further reduces the leakages, in particular GIDL) by SEE-DM-SG MOSFET is deeply studied and investigated by analyzing band energy across the valence and conduction bands.