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Bit-Width Allocation for Hardware Accelerators for...
Journal article

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

Abstract

This paper investigates the application of computational methods via Satisfiability Modulo Theory (SMT) to the bit-width allocation problem for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. In contrast to the large body of work targeted at the precision aspect of the problem, this paper addresses the range problem where employing SMT leads to more …

Authors

Kinsman AB; Nicolici N

Journal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 3, pp. 405–413

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publication Date

March 1, 2010

DOI

10.1109/tcad.2010.2041839

ISSN

0278-0070