Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation

Once a bug is found during post-silicon validation, before committing to a silicon respin of the design it is expected that any other bugs, which have escaped pre-silicon verification, to be also identified. This will minimize the number of respins, which in turn will reduce the implementation costs. However, this is hindered by the presence of blocking bugs in one erroneous module that inhibit the search for bugs in other parts of the chip that process data received from this erroneous module. To address this problem, in this paper we propose a novel embedded debug architecture for bypassing the blocking bugs when dealing with deterministic debug experiments.