A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning

The number of speedpaths in modern high-performance designs is in the range of millions and, due to unmodelled electrical effects, they are difficult to be measured accurately before the first silicon samples are available. As a consequence, clock tuning elements are employed to aid the post-silicon clock tuning. However, as the number of these elements continues to grow, it becomes increasingly difficult to determine their configurations in a compute effective manner. In this paper we describe a novel exact algorithm for post-silicon clock tuning, which employs smart pruning techniques that exploit the characteristics of the clock tuning buffers.