Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

It was found that, as the channel length decreased, the threshold voltage shift caused by drain-induced barrier lowering (DIBL) first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (L/sub INT/) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 and 0.90 mu m for the PMOS devices. This change in DIBL with substrate …