Special Issue on Compact Interconnect Models for Gigascale Integration

This special Issue is devoted to research and development activities on emerging compact interconnection models for advanced circuit simulation using next-generation silicon technology and beyond. The continuous scaling of CMOS devices to the sub-90-nm regime has resulted in higher device density, faster circuit speed, and lower power dissipation. As VLSI technology shrinks below 90-nm geometries with Cu/low- $k$ interconnections, parasitics due to interconnections are becoming a limiting factor in determining the circuit performance. Therefore, accurate modeling of interconnection parasitic resistance (R), capacitance (C), and inductance (L) is essential in determining various on-chip interconnect-related issues, such as delay, crosstalk, IR drop, and power dissipation. Accurate compact interconnection models are crucial for the design and optimization of advanced VLSI circuits for 65-nm CMOS technology and below. In addition, with the emergence of technologies such as carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), compact interconnection models that are suitable for these technologies are crucial for advanced circuit design. Currently available interconnection models, which are based on field solvers, are inadequate for accurate and meaningful analysis of today's chip with millions of devices.