Journal article
Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime
Abstract
The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.
Authors
Marinov O; Deen MJ
Journal
IEEE Electron Device Letters, Vol. 30, No. 8, pp. 840–842
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Publication Date
August 1, 2009
DOI
10.1109/led.2009.2023382
ISSN
0741-3106