Generating stacking faults in 4H–SiC junction transistor by indentation and forward biasing

Stacking faults in silicon carbide have been widely studied due to their negative impact on the application of silicon carbide in the power electronics industry. In this work, with the assistance of forward biasing, we observe several triangular shaped structures emerging near the indenter imprint in two separate 4H–SiC bipolar junction transistor samples that were deformed by nanoindentation. Based on the study of electroluminescence spectra on one of the samples, the emission peak at 420 nm indicates the formation of single Shockley stacking faults inside deformed transistors. We conclude that the use of indentation can provide a method to study recombination induced stacking faults in silicon carbide junction devices by intentionally introducing dislocations at selected areas of interest.