Foreword Special Issue on Compact Modeling of Emerging Devices

THIS Special Issue is devoted to the recent research and development in compact models (CMs) of emerging devices for circuit simulations. Since the previous Special Issue on advanced compact models and 45-nm modeling challenges in September 2006, the technology has moved from planar bulk CMOS toward vertical FinFETs that are essentially short-channel, narrow-width, and thin-body transistors. New devices, such as organic, junctionless, tunneling, and III–V channel field-effect transistors (FETs), are also emerging. Since the pioneering work of the 1966 Pao–Sah double integral for MOSFETs and the 1970 Gummel–Poon BJT model (who~coined CM), and the advent of the SPICE circuit simulator, we have witnessed several generations of CMs being developed and used in designing ULSI circuits over the past decades. We are now at the intersection of viewing (reviewing) and modeling these nanoscale transistors from two different perspectives: 1) continuing to add quantum and ballistic effects into the conventional drift–diffusion and velocity-saturation based formalism, or 2) starting to formulate quasi-ballistic-based equations while adding scattering effects for modeling real devices that are somewhere in between.