Universal CMOS gate for parallel test of logic circuits

With the increasing complexity of integrated circuits, the cost of testing is on the rise. Design for testability methodologies with the introduction of extra hardware tries to reduce different cost factors associated with the testing of a complex circuit at the expense of added chip area. In this paper, a novel universal gate is proposed for the complete testability of combinational circuits. Also, an algorithm is devised to perform the simple testing of sequential circuits. The ease of testing, using the proposed structure, is independent of the size and complexity of the circuit. Two different designs using CMOS technology are proposed. © Sharif University of Technology, October 2003.