FPGA‐based system for effective IQ imbalance mitigation of RF power amplifiers

Summary To provide an adequate signal integrity to a power amplifier (PA), we propose a digital system for the degradation at the transmitter path, and it is implemented on a field‐programmable gate array (FPGA) board. The proposed system offers the following features: A ‐ary quadrature amplitude modulation (QAM) digital signal generation and in‐phase/quadrature (IQ) imbalance mitigation, and by default, it performs as a predistortion model extraction from PA‐measured data. The simulations and tests provided are performed to effectively verify the PA linearity by using 256‐QAM signals. The nonlinearities are predicted as a reliable solution for linearizing the PA from measurements of AM/AM and AM/PM conversion curves. The performance is evaluated in terms of linearity, computation complexity, and FPGA hardware synthesis according to a dependability compliance of digital signal processing. Finally, the model is validated with input/output data observations to linearize the model with a fitting normalized mean squared error (NMSE) of around  dB, a spurious free dynamic range of 40 dBm, and an adjacent channel power ratio reduction by  dBm, for a class‐AB broadband radio frequency PA GaN HEMT of 10 W working at 2.34 GHz.