Active stabilisation design of DC–DC converters with constant power load using a sampled discrete‐time model: stability analysis and experimental verification

Instabilities of cascade converters with an LC filter in between in power electronic systems have been known, and many answers have been proposed. The load converters are tightly regulated, acting as constant power loads (CPLs). Average models are generally utilised to study the behavior of the converters. For embedded applications, the weight and the volume should be reduced. Consequently, in this case, the limitations of the average method are reached when the cut‐off frequency of the LC input filter is close to the switching frequency. Then, other tools are necessary to study this type of system. To overcome this problem, a discrete‐time model was developed to study the behavior of the system, taking into account the switching effect. The aim was to enlarge the power range of the stability zone for a DC system composed of a DC–DC boost converter as a source converter, which was connected to the power load via an LC input filter. For this purpose, a stabilisation expression is integrated in the command of the source converter. The stability analysis by the eigenvalues of the system is described using the proposed model. Simulation and experimental results are discussed to verify the proposed stabiliser in different cases.