Structuring of Contourlet Transform for Pipeline-Based Implementation

Contourlet transform (CT) is a powerful image processing tool. Even though many promising applications have been proposed, no hardware implementation of CT has been reported. This paper analyzes CT to form a structure which is hardware implementable. CT consists of two main parts, Laplacian pyramid (LP) and directional filter bank (DFB). In both parts, novel algorithmic changes are proposed for realizing efficient hardware architecture. In the proposed LP structure, 50 % of the arithmetic operations have been reduced and it operates twice as fast as the existing implementations. To the best of our knowledge, DFB has not comprehensively been studied for hardware implementation so far. Thus, we first analyze DFB to figure out its hardware-oriented structure and then propose DFB architecture. Finally, analysis and simulation results demonstrate that the proposed CT architecture achieves the real-time performance (40 frame/s) operating at 76 MHz which is verified through FPGA implementation. Moreover, since all stages utilize fixed-point arithmetic operations, the comprehensive quantization analysis is performed to keep the MSE and PSNR values in an acceptable range.