Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal–oxide–semiconductor field effect transistor channels

Si/Si 0.64 Ge 0.36 /Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically …