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Extraction of Gate Resistance in Sub-100-nm...
Journal article

Extraction of Gate Resistance in Sub-100-nm MOSFETs With Statistical Verification

Abstract

This paper presents an improved z-parameter based approach to extract the gate resistance at low frequencies. The effectiveness of this approach, compared with other y-parameter based approaches, is verified using 430 samples fabricated in 40-, 55-, 90-, and 110-nm CMOS technology nodes. The influence of the nonquasi-static (NQS) effect, resulting from the distributed channel resistance, on the gate resistance extraction is studied, and the …

Authors

Chen X; Tsai MK; Chen C-H; Lee R; Chen DC

Journal

IEEE Transactions on Electron Devices, Vol. 61, No. 9, pp. 3111–3117

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

DOI

10.1109/ted.2014.2340871

ISSN

0018-9383