Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications Academic Article uri icon

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abstract

  • Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

authors

  • Kirk, Andrew G
  • Plant, David V
  • Szymanski, Ted
  • Vranesic, Zvonko G
  • Tooley, Frank AP
  • Rolston, David R
  • Ayliffe, Michael H
  • Lacroix, Frederic K
  • Robertson, Brian
  • Bernier, Eric
  • F. Brosseau, Daniel

publication date

  • May 10, 2003