Sampled-data controller implementation

The setting of this article is the implementation of timed discrete-event systems (TDES) as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states and updates its outputs. In this article, we establish a formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We …