Sampled-data controller implementation

The setting of this article is the implementation of timed discrete-event systems (TDES) as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states and updates its outputs. In this article, we establish a formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We describe how to translate a TDES supervisor to an FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralised controller as well as a set of modular controllers, and show that they will produce equivalent output. We briefly discuss how the recently introduced SD controllability definition relates to our translation method. SD controllability is an extension of TDES controllability which captures several new properties that are useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We next discuss the application of SD controllability to a small flexible manufacturing system (FMS) from the literature. The example demonstrates the successful application of the new SD properties. We describe the design of the system in detail to illustrate the new conditions and to provide designers with guidance on how to apply the properties. We also present some FSM translation issues encountered, as well as the FSM version of the system's supervisors.