Parallel parasitic conductance in narrow-width MOSFETs

One of the edge effects of narrow-width MOSFETs can be expressed as a parallel parasitic conductance GP. GP And the width reduction ΔW were determined from the variation of device's conductance GT vs mask gate width WM at different effective gate biases VGS − VT. The intersection point of these GT vs WM for different VGS − VT biases occurs at GP and ΔW. A series of experiments in which external conductances were placed in parallel with the MOS transistor were performed, and the results verified the concept of the parallel parasitic conductance, and the algorithm for extracting both GP and ΔW.