Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation

Optimum design of input matching network of CMOS low-noise amplifiers (LNAs) for low-power applications is discussed in this paper. This is done through an investigation of the effect of four different matching methodologies on the gain of radio frequency CMOS LNAs by means of compact analytical expressions. It is demonstrated that methods that convert the MOSFET's input impedance to 50 $\Omega$ for power matching are more suitable for low-power applications than methods that create a real 50-$\Omega$ resistance at the input of the LNA, such as source inductive degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET's input resistance. The impact of each matching methodology on the noise figure (NF) of the LNA is also discussed in detail and design guidelines for optimum gain-NF performance are developed using analytical models of MOSFET's noise parameters. It is demonstrated that all four methods could achieve very good NF values, provided that the size of active and passive components are chosen carefully based on the given guidelines. Measured results of two monolithic 5.7-GHz LNAs, designed and fabricated in a 0.18-$\mu$m CMOS technology, are also presented. The input matching networks of these LNAs are optimized for low-power operation based on the theory presented in this paper. It is experimentally shown that this optimization results in approximately 60% reduction in the dc power consumption and up to 300% improvement in the overall performance of the LNA when compared with some of the most recently published LNAs.